An efficient MAC unit with low area consumption

In this paper we propose a new architecture for an efficient MAC (Multiplier Accumulator Unit) unit with low area consumption which includes Vedic Square as an alternate component in the MAC unit. Vedic Square is based on the principle of Duplex property of Urdhva Tiryagbhya. Using the proposed architecture, 50% of logic gates are reduced from the basic level of 2*2 bit and 12.64% from 16*16 bit square computation. Hence, speed is increased by means of decreased toggling of gates. This also reduces total area of the MAC unit by 11.23% as compared to the MAC with Vedic Multiplier and Kogge Stone Adder (when run for computations of square). The overall performance of MAC unit is determined by three parameters, namely speed, power and area. The proposed architecture of High speed and low area consumption MAC unit would contribute immensely to the future DSP systems. Mentor Graphics-Modelsim 6.5a PE and Precision synthesis by Mentor Graphics are used for implementation.