Merits of designing Tunnel Field Effect Transistors with underlap near drain region

In this paper, electrical characteristics of three different types of TFET architectures have been studied by creating an underlap near drain region. Both gate and dielectric alignment effects have been studied in terms of parasitic capacitance values where all three architectures have been compared with the conventional p-i-n TFET. Subsequently, underlap length variations in forward (on-state) and reverse (accumulation state) gate bias regimes have been investigated. It has been revealed that creating underlap region using both gate and dielectric seems to be a better option which can further be improvised by using a pocket doped TFET architecture.