Design and simulation of high speed comparator for LVDS receiver application

Nowadays, instead of manufacturing IC in a single package, they are manufactured in multiple packages with all integrated internally through buses (or) wires to transfer the data. It helps in reducing the complexity and as well as makes easy to replace only the faulty module instead of complete IC. The feature size as well as supply voltage of IC´s are decreasing day by day with the aim of decrease in power consumption, increase in operational speed and as well as cost. Thus, data can be transmitted among themselves with the help of different signaling techniques. Amongst the various signaling techniques used, differential signaling is the most preferred technique at IC level. Low Voltage Differential Signaling (LVDS) is the best compromise between the speed, cost and power consumption. At the first stage of the LVDS Receiver, a comparator has to be used. As the comparator is one of the block which limits the speed of the receiver, its optimization is of utmost importance. In this, pre-amplifier based latched comparators are used for attaining a frequency more than 2 GHz.