A low voltage high speed DCVSL based ring oscillator

In this paper, a high speed Differential Cascode Voltage Switch Logic (DCVSL) architecture has been proposed. Conventional DCVSL has higher τ_PLH than τ_PHL which limits its switching speed. Use of resistive enhancement technique, DCVSL-R can overcome the inherent delay asymmetry problem of DCVSL but the passive resistors used increase its parasitic capacitances as well as require more physical area for on-chip implementation. To remove this drawback, Bidirectional MOS resistors have been used in the proposed DCVSL configuration. Performance of the logic is analyzed using ring oscillator circuit which is operating at 1.815 GHz frequency in the RF range. The circuit is simulated at 1.2V supply voltage using BSIM3V3 180nm CMOS technology. Simulations have been performed using Agilent´s Advanced Design System tool.