Power efficient design of a novel SRAM cell with higher write ability

The modern high-performance portable communication devices are the key to make the world more inclusive than before. There is a great demand for high-performance SOC inside the high-performance portable devices. According to ITRS and current research, on chip memory technology plays a great role in the SOC performance. Hence enhancing on-chip memory performance will lead to performance enhancement of the device. A novel SRAM cell is designed which reduces the total power consumption by 15.33%. It also increases the write-ability by 63.61% with respect to the conventional 6T-SRAM cell. It blocks the short-circuit current during state transition to reduce the dynamic power consumption. During a write operation, it initiates the feedback loop process for data latching, earlier than the 6T-SRAM cell which increases the write-ability of the proposed cell by a large amount. A thorough analysis about power consumption, write-ability and physical layout design of the proposed cell array is carried out and compared with that of a conventional 6T-SRAM cell array.