Comparative study of performance vedic multiplier on the basis of adders used

Vedic multiplier is an efficient system for faster result and optimized circuit design. Maintaining higher throughput in arithmetic operations is important to achieve the desired performance in many real-time applications. One of the key arithmetic operations in such applications is to achieve faster multiplication. Vedic Mathematics is one of the fast and low power multiplier. In the present paper, area, delay and power of a Vedic multiplier is taken into consideration for the comparison. The results that were taken for comparison has previously done and here that results were constituted in this paper for comparative study to choose the better adder. These parameters are compared for different adders such as Carry look ahead adder(CLA), Carry select adder(CSLA), Ladner Fischer adder(LFA), Brent Kung adder(BKA), Kogge Stone adder(KSA) and compressors in Vedic multiplier. The number of adders can be minimized by using special adders called compressors which can add more number of bits at a time. This paper gives information of Urdhva Tiryakbhyam algorithm of Vedic Mathematics which is utilized for multiplication to improve the speed and area of multipliers. The power consumption of vedic multiplier depends on the type of the adder used so a comparison which has already done in RTL Cadence compiler is taken for the comparative study here.