A fast acquisition phase frequency detector for high frequency PLLs

The delay of the reset path, needed to eliminate the dead zone problem in a conventional three-state phase frequency detector (PFD) limits the maximum frequency at which the circuit can operate as well as the linear input range for which the circuit provides gain. For large phase errors between the two inputs, a conventional PFD can lead to outputs with wrong polarity which delays the acquisition process of the phase locked loop (PLL). A new pulse-clocked PFD is presented which maximizes its linear input range (-2π to 2π). This reduces the probability of missing clock cycles and hence leads to faster acquisition of the lock in a PLL. This PFD also works at a higher input clock frequency which is required for PLLs generating microwave or millimeter-wave frequencies. The PFD is implemented in 0.13 μm CMOS technology.