Fault analysis of QCA combinational circuit at layout & logic level

QCA (Quantum-dot Cellular Automata) is the most capable future nanotechnology for computing. Defects are most likely to occur in QCA devices due to the nanoscale Faults caused by these defects must be analyzed. This paper implement the QCA combinational circuit, half adder for which fault analysis is carried out. This paper presents the fault analysis of QCA combinational circuit, half adder at layout level using QCADesigner tool and at logic level using Hardware description Language for QCA (HDLQ).