DocumentCode :
3765453
Title :
The effect of gate layout on responsitivity of MOSFET THz detector
Author :
P. Kopyt;D. Obrebski;P. Zagrajek;J. Marczewski
Author_Institution :
Institute of Radioelectronics, Warsaw University of Technology, Warsaw, Poland
fYear :
2015
Firstpage :
1
Lastpage :
2
Abstract :
In this paper an attention is paid to the existence of parasitic elements in a typical n-channel MOSFET devices that are often employed in sub-THz detectors and the role they play in when such devices are employed at sub-THz frequencies. An effective circuit model of such a structure was constructed. The most of the effort was put to investigate the influence of the layout of the MOSFET´s Gate on the expected responsivity of the detector. In particular, attention was paid to the contacts between the metallization layer (MET) that connects the Gate to the outside world, and the polysilicon (POLY) layer that forms the actual Gate in a typical MOSFET.
Keywords :
"Logic gates","MOSFET","Capacitance","Detectors","Semiconductor device modeling","Integrated circuit modeling","Layout"
Publisher :
ieee
Conference_Titel :
Infrared, Millimeter, and Terahertz waves (IRMMW-THz), 2015 40th International Conference on
ISSN :
2162-2027
Electronic_ISBN :
2162-2035
Type :
conf
DOI :
10.1109/IRMMW-THz.2015.7446236
Filename :
7446236
Link To Document :
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