A scalable bootloader and debugger design for an NoC-based multi-processor SoC

This paper presents bootloader and debugger architectures that are designed for an NoC-based Multiprocessor System On-Chip (MPSoC). An MPSoC demands scalable bootloader and debugger architectures, especially with the increasing of the number of the processor cores. The proposed bootloader and debugger designs utilize the NoC interconnect network to distribute data to and from the cores. With this design approach, the bootloader and debugger require relatively small hardware overhead and are able to fully utilize the benefit of the NoC architecture´s scalability.