Title :
A study of the effect of virtual channels on the performance of Network-on-Chip
Author :
Adusumilli Vijaya Bhaskar;Tiruchirai Gopalakrishnan Venkatesh
Author_Institution :
Department of Electrical Engineering, Indian Institute of Technology Madras, Chennai, India
Abstract :
Network-on-Chip (NoC) is the communication backbone of multi-core and many-core processor architectures. Wormhole flow control is the commonly used flow control mechanism in on-chip interconnection networks, however it causes head-of-line blocking as network load increases which can be solved using virtual channel flow control. In this paper we investigate the effect of Virtual Channels (VC) on the performance of NoC by varying injection rate, traffic pattern and the packet length. We simulate an 8×8 mesh network with dimension order routing. Synthetic workloads are used to find the effect of virtual channels on throughput and latency. We show that as the number of virtual channels is increased there is an improvement in the throughput and latency of the network up to a certain number of virtual channels beyond which the network reaches saturated state. Our work can be used as a guidance to find the optimal number of virtual channels for a given NoC configuration and traffic parameters.
Keywords :
"Throughput","Delays","System-on-chip","Switches","Routing","Network topology","Topology"
Conference_Titel :
Research and Development (SCOReD), 2015 IEEE Student Conference on
DOI :
10.1109/SCORED.2015.7449335