DocumentCode
3766992
Title
Design and characterization of three stage CMOS op amps in 130nm technology with indirect feedback compensation technique
Author
H. Guliga;S.H. Herman;W.F.H. Abdullah
Author_Institution
Faculty of Electrical Engineering, Universiti Teknologi MARA (UiTM), 40450, Shah Alam, Selangor, Malaysia
fYear
2015
Firstpage
605
Lastpage
609
Abstract
This paper presents the three stage CMOS operational amplifier (op amp) with class A output stage designed in SilTerra´s 130 nm CMOS technology. The designed three stage op amp employed an indirect feedback compensation technique produces an open loop gain (AOL), for both schematic and layout are 102 dB and 117 dB respectively. the op amp produces 40.5 MHz gain-bandwidth product (GBW), 90° phase margin(PM) and 54.6 V/μs slew rate (SR) for 5 pF load. Furthermore, the op amp has capability to drive the 15 pF load, produces 25.5 MHz GBW and 45° PM. The circuit was operated at the single supply voltage of 2.5 V with power consumption of 0.977 mW and the layout area was 0.0022 mm2.
Keywords
"Operational amplifiers","Layout","Gain","CMOS integrated circuits","CMOS technology","Capacitance","Conferences"
Publisher
ieee
Conference_Titel
Research and Development (SCOReD), 2015 IEEE Student Conference on
Type
conf
DOI
10.1109/SCORED.2015.7449408
Filename
7449408
Link To Document