Design of a low power 0.25 ?m CMOS comparator for sigma-delta Analog-to-Digital Converter

A CMOS comparator using dynamic latch, suitable for high-speed Analog-to-Digital Converter (ADC) with high speed and low power dissipation is presented. The design is intended to be implemented in Sigma-delta ADC. This circuit combines the good features of the resistive dividing comparator and the differential current sensing comparator. The design has been carried out in Tanner EDA tools, the schematic simulation is done using Schematic Editor (S-Edit) and layout simulation of the design is verified using Layout Editor (L-Edit) using 0.25μm CMOS technology. Simulation results are done with supply voltages of 1.6V, 1.8V and 2.0V respectively. It is found that the power is least dissipated in 1.6V which is 0.7899 mW, but it has the longest propagation delay of 0.715 ns. In contrast, the 2.0V supply produced 1.471 mW and a shorter delay of 0.550 ns.