DocumentCode
3767275
Title
Effect of gate length variation on DC performance of Ino.7Gao.3As/InAs/Ino.7Gao.3As composite channel HEMT
Author
Dilip Jaiswal;Nandkishor Chavan; Kulshrestha;Hemant Pardeshi
Author_Institution
Department of Electronics Engg., Jodhpur National University, Jodhpur, India
fYear
2015
Firstpage
181
Lastpage
184
Abstract
In this paper we have analyzed the effect of gate length variation on the DC parameters of In0.7Ga0.3As/InAs/In0.7Ga0.3As composite channel HEMT using 2D Sentaurus TCAD simulation. Hydrodynamic model is used for the simulation. The simulation model is calibrated with the previously published experimentally. Extensive device simulation of major device performance metrics such as drain induced barrier lowering, subthreshold slope, delay, threshold voltage, ON current to OFF current ratio and energy delay product have been done for wide range of gate length. As gate length is scaled the heterostructure devices using composite channel, with high-k dielectric provides higher ON current, lower delay and energy delay product. With gate length scaling there is a moderate increase in short channel effects such as DIBL, and SS. The result indicates the need to improve the Ion/Ioff ratio, Vt and SS as these are deviating slightly from the desired results. The proposed composite channel HEMT shows excellent promise as one of the candidates for future high speed applications.
Keywords
"Logic gates","HEMTs","Delays","Numerical models","Analytical models","Performance evaluation","Semiconductor process modeling"
Publisher
ieee
Conference_Titel
Computer Graphics, Vision and Information Security (CGVIS), 2015 IEEE International Conference on
Type
conf
DOI
10.1109/CGVIS.2015.7449918
Filename
7449918
Link To Document