• DocumentCode
    3767361
  • Title

    Hardware Design and Verification Techniques for Supply Chain Risk Mitigation

  • Author

    Bao Liu;Yier Jin;Gang Qu

  • Author_Institution
    Electr. &
  • fYear
    2015
  • Firstpage
    238
  • Lastpage
    239
  • Abstract
    We present a brief survey on the state-of-the-art design and verification techniques: IC obfuscation, watermarking, fingerprinting, metering, concurrent checking and verification, for mitigating supply chain security risks such as IC misusing, counterfeiting and overbuilding.
  • Keywords
    "Integrated circuits","Hardware","Watermarking","Supply chains","Design automation","Foundries"
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design and Computer Graphics (CAD/Graphics), 2015 14th International Conference on
  • Type

    conf

  • DOI
    10.1109/CADGRAPHICS.2015.53
  • Filename
    7450435
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3767361