Design and implementation of 15-4 compressor using 1-bit Semi Domino full adder at 28nm technology

In this paper, a 15-4 Compressor for Low power arithmetic operations is presented. A new Low power full adder and 5-3 compressor are used in this 15-4 compressor. Full Adder and 5-3 compressors are realized by Semi Domino logic which is faster and consumes less power than other conventional logics. Objective of this work is to study the power, delay, power delay product of full adders in different logic styles and to study the power, delay, and power delay product of Semi Domino 5-3 compressor architecture with other architectures. Simulation results demonstrate the superiority of the proposed adder circuit against the previous adder circuits in terms of power, delay, PDP. The proposed style gets its benefit in terms of power, delay, PDP. The performance of the adder circuits and compressors is based on TSMC 28nm CMOS process models at the supply voltage of 1V evaluated by comparing of the simulation results obtained from Cadence spectre.