Title :
A comparative study of 6T-SRAM cell designed using Symmetrical Double Gate MOSFET and Symmetrical Double Gate Ferroelectric FET
Author :
Mulaka Haranadha Reddy;Srivatsava Jandhyala
Author_Institution :
Centre for VLSI Design and Embedded Systems, International Institute of Information Technology, Hyderabad, India-500032
Abstract :
Scaling is aggressively performed for SRAMs to improve the memory integration density. At advanced technology nodes, 6T-SRAM cells built using Symmetrical Double Gate (SDG) MOSFETs are shown to perform better than those built with bulk MOSFETs. Recently the Symmetric Double-Gate Ferroelectric Field Effect Transistor (SDG-FeFET) has generated considerable interest since it has the potential to reduce the Subthreshold Swing (SS) of a transistor below the classical Boltzmann´s limit. This was achieved exploiting the negative capacitance behavior of Ferroelectric Material which resulted in reduction of the power and delay of the transistor. In this paper, we simulate a 6T-SRAM cell using SDG-FeFETs and do the comparative study of its performance with SDG MOSFETs as a function of supply voltage and cell ratios. 6T-SRAM cell using SDG-FeFETs is shown to offer significant improvement in the read and write access times and marginal improvement in corresponding static noise margins (SNMs) as well, making it a attractive option for future technology nodes.
Keywords :
"MOSFET","SRAM cells","Logic gates","Stability analysis","Capacitance"
Conference_Titel :
Microelectronics and Electronics (PrimeAsia), 2015 IEEE Asia Pacific Conference on Postgraduate Research in
Electronic_ISBN :
2159-2160
DOI :
10.1109/PrimeAsia.2015.7450468