DCT and CORDIC on a novel configurable hardware

Discrete Cosine Transform (DCT) operations, used in compression algorithm, have great significance in image and signal processing applications where the cosine computation forms an integral part. The CORDIC (COrdinated Rotation Digital Computer) algorithm provides a simplistic and accurate platform to compute various trigonometric, linear and non-linear functions using only shift-add operations. Due to inherently repetitive nature of DCT and CORDIC function, it yields to efficient hardware implementations. This paper presents the implementation of DCT and CORDIC on a novel configurable architecture ported onto a state of the art FPGA. The proposed architecture uses only shifts and adds to perform multiplication, thereby reducing the gate count. The design takes 192 clock cycles and 336 clock cycles/image block to compute cosine using CORDIC and DCT, respectively. The L2 norm of the hardware reconstructed image is 15.77 at 84.37% compression on a 128×128 image and computes cosine (CORDIC) with accuracy upto 98%.