DocumentCode
3767887
Title
The fault-tolerant NoC techniques with FPGA
Author
Zhi Lu;Shu Yan Jiang;Le Tian Huang;Chao Wu;Gang Luo;Qi Li;Guo Ming Song
Author_Institution
School of Automation Engineering, University of Electronic Science and Technology of China, Chengdu 611731, China
fYear
2015
Firstpage
54
Lastpage
55
Abstract
In this paper, we mainly study the key technical issues of Network-on-Chip (NoC), focusing on the analysis of typical NoC mapping problems, and making further research on the fault-aware NoC task mapping. Firstly, we study some critical problems in the design of NoC task mapping, then summarized a fault model, and finally, verified the related issues of NoC on verification platform and Field Programmable Gate Array (FPGA).
Keywords
"Field programmable gate arrays","Circuit faults","Fault tolerance","Fault tolerant systems","IP networks","Transient analysis","Routing"
Publisher
ieee
Conference_Titel
Applied Superconductivity and Electromagnetic Devices (ASEMD), 2015 IEEE International Conference on
Print_ISBN
978-1-4673-8106-2
Type
conf
DOI
10.1109/ASEMD.2015.7453463
Filename
7453463
Link To Document