Design of energy efficient semi-serial on-chip communication link

Low energy semi-serial on-chip communication link is to be designed. This link is designed using high speed serialization/deserialization and pulse dual rail encoding techniques. The link also consists of wave-pipelined differential pulse current-mode signaling to maintain the high speed data intake from the serializer. The energy efficiency of the proposed semi-serial link, which consists of bit serial links in parallel, mainly comes from sharing of serializer´s control circuit among the bit-serial links. In addition, the integration of pulse signaling with wave-pipelining, the use of a new low-complexity data validity detection technique, and the avoidance of data decoding logic also contribute to power reduction.