Abstract :
The radar systems have been so significant for both civil use and national defense, and adopting localized processor has become critical for a country, especially for the area related to the national defense. In this paper, we utilize localized BWDSP100 as the main processor, and implement a high-speed and real-time signal processing system by using BWDSP100 + FPGA framework. We use FPGA to realize the interface conversions and extensions, which enhance the reading bandwidth of the DDR2 interface from 235MB/s to 562MB/s. Besides that, we also integrate highspeed serial buses, such as PCIe interface of 243MB/s and SRIO interface of 344MB/s, for communications in or between boards. The system has been used in several projects, and works well.
