DocumentCode :
3769386
Title :
The implement of spaceborne SAR imaging system
Author :
Li Yan;Zhao Boya;Chen Liang;Chen He;Wang Tao
Author_Institution :
General Department, China Academy of Space Technology, Beijing 100048, China
fYear :
2015
Firstpage :
1
Lastpage :
4
Abstract :
With the rapid development of FPGA parallel processing and DSP float-point computing capability, FPGA and DSP play an increasingly important role in the field of high-speed real-time synthetic aperture radar (SAR) signal processing system. In this letter, based on the SAR imaging needs and principles, taking chirp scaling algorithm for example, we design a spaceborne SAR real-time imaging heterogeneous system implemented by FPGA and DSP. The heterogeneous system uses modular thinking, pipeline and parallel processing techniques, which greatly improves the speed and operation precision in SAR imaging. Besides, the SAR imaging system has a good realtime performance, scalability and faulty tolerance and can well meet the needs of spaceborne SAR imaging system. The system needs 19.72s to generate a 4096*4096 pixel image.
Publisher :
iet
Conference_Titel :
Radar Conference 2015, IET International
Print_ISBN :
978-1-78561-038-7
Type :
conf
DOI :
10.1049/cp.2015.1317
Filename :
7455539
Link To Document :
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