Design of a large point FFT processor with configurable transform length

In this paper, a scheme of a large point FFT processor with configurable transform length is proposed. To achieve a pipelined structure, the proposed scheme is designed by Radix-2 decimation-in-frequency (DIF) FFT algorithm with Single-path Delay Feedback (SDF) architecture. A prototype is implemented on Xilinx Virtex-7 XC7VX690T FPGA, which can compute 16~128K FFT at a speed as high as 350MHZ.This scheme is superior to existing technologies, due to its ability to process a continuous-flow input sequence and its prospect for real-time, configurable transform length applications.