Study and reduction of variability in 28 nm FDSOI technology

This In this paper, we present a new inverter topology in order to decrease the process variability influence on performances of a ring oscillator. Using FDSOI technology, we used the back-gate electrode of the transistor to symmetrize the output of a complementary inverter. This technique will reduce the variability of the inverter and the jitter (i.e. the phase noise) of the ring oscillator. Complementary cells allow us to implement back-gate auto-biasing feedback without adding transistors and to realize a quadrature ring oscillator with an even number of inverters.