Test bench automation to overcome verification challenge of SOC Interconnect

With the increasing number of Intellectual Property (IP) cores in the todays system on chip (SOC), verification of Interconnect Bus matrix becomes a critical and time consuming task. Development of verification platform for complex SOC Interconnect takes several weeks considering it supports different kinds of protocol, large number of master and slave ports with multiple transaction types. To reduce overall time-to-market for SOC delivery, it is crucial to verify Interconnect in a very narrow time frame. In this research article, we present Test Bench(TB) automation solution for verifying completeness and correctness of data as it pass through interconnect fabric. Automation reduces verification effort by automatically creating authenticated infrastructure, stimulus vector and coverage model to support all transactions exchanged between Masters and Slaves within an SOC. This approach enables a protocol independent scoreboard to check data integrity and verify different data path transactions fo and from each port of bus fabric. We applied the proposed solution to various bus matrix testing which lead to 40% save in verification cycle.