Implementation of 10bit SerDes for Gigabit Ethernet PHY

Serializer/Deserializer (SerDes) is a pair of functional block which play a vital role in many electronic devices used for high speed communication. The basic SerDes function is made up of two functional blocks: the Parallel In Serial Out (PISO) block and the Serial In Parallel Out (SIPO) block. An efficient SerDes offer high speed and low power consumption. In this paper an attempt is made to optimize the design for high speed and low power SerDes for wideband communication such as Ethernet applications. The power consumption and data transfer rate of the proposed design was calculated to be 737 mWand 25Gb/s respectively.