A novel low power, high performance design technique for domino logic

Domino logic circuits are most often used in high performance designs such as microprocessors because of high speed and less area over the static logic. But these domino logics suffer from high power dissipation and low noise tolerance. In this paper the earlier proposed techniques to reduce power consumption of Domino logic such as Dual Threshold Voltage (DTV), Dual Threshold Voltage-Voltage Scaling (DTVS) and Stacked Transistor Dual Threshold Voltage (ST-DTV) are analyzed. A novel technique using Dual Threshold Voltage technique with Stacked Transistor only in pull-up path along with Voltage Scaling and Charge Sharing technique is proposed in this paper. The proposed technique gives smaller power dissipation with better Power Delay Product (PDP) compared to earlier power reduction techniques. The gate length biasing technique can be used to further reduce the leakage power. The impact of gate length biasing on the proposed design is shown in the later part of the paper. The proposed design is simulated using 3 input OR gate at 28 nm bulk CMOS technology. The simulations are performed with Mentor Graphics ELDO 13.2 and EZ-wave simulators.