FPGA implementation of BCH decoder for memory systems

BCH (Bose-Chaudhuri-Hocquenghem) coding is very useful to detect and correct the errors in communication system and also on-chip (computer) memory systems. This paper presents a High-speed BCH decoder that corrects double-adjacent and single-bit errors in parallel and serially corrects multiple-bit errors instead of double-adjacent errors. Its operation is based on extending an existing decoder that corrects only single-bit errors in parallel and serially corrects double-adjacent errors at low speed. The proposed constructed decoder design is suitable for nanoscale memory systems, in which double-adjacent and single-bit errors occur at a higher probability compared to the multiple-bit errors. This paper also shows that the area and delay overheads incurred by the proposed scheme are significantly lower than traditional BCH decoders capable of correcting any double-bit errors in parallel.