A 16 Mb RRAM test chip based on analog power system with tunable write pulses

One transistor one resistor (1T1R) structure can be used to suppress the sneak current in RRAM array. In this paper, a 16Mb 1T1R RRAM chip is proposed. The 130 nm HH-Grace process is used as the FEOL of the chip. A HfOx/CMO based RRAM stack will be fabricated using back end process. The chip mainly contains four blocks: the RRAM array, the analog power block, the control logic block and the pad ring which uses standard pad provided by foundry. The operating conditions is designed to be configurable to explore different RRAM stack. Tunable write pulses can be used to improve the RRAM performance. The analog power system supplies different voltage levels to achieve specific function. The simulation results show that the chip can work as expected.