Power saving technique for thermometer-code digital-to-analog converters

The current-steering architecture is widely used in high-speed DACs, since this architecture has good linearity at high speed. Therefore, this thesis adopts the current-steering architecture to design the DAC in order to achieve the high-speed application. The power saving technology for the thermometer-code DAC is proposed in the thesis. This technique can reduce the power consumption and the clock feedthrough. Instead of the traditional design, which using clock signal to update all current cells in each period, this design detects the data variation first and then only update the current cells which actually change the data. The proposed design can save the power consumption produced by the latches switched. Finally, the design was simulated in TSMC 90nm CMOS process. The sample rate and resolution of the DAC are 1GS/s and 12-bit, respectively. The power consumption is 30mW. The simulation results show that the proposed power saving technology can save power consumption. Even in the worst case, this technique can still save 10% power consumption.