DocumentCode :
3770923
Title :
Utilizing Ge interlayer and patterned substrate to improve the contact resistance of n-GaN
Author :
Ting-Wei Liao; Chien-Wei Chiu; Chieh-Hsiung Kuan; Tsung-Yi Huang; Tsung-Yu Yang
Author_Institution :
Graduate Institute of Electronics Engineering, Department of Electrical Engineering, No. 1, Sec. 4, Roosevelt Road, Taipei, 10617, Taiwan, China
fYear :
2014
fDate :
7/1/2014 12:00:00 AM
Firstpage :
1
Lastpage :
3
Abstract :
This paper is demonstrated the effect of Ge interlayer and patterned substrate to form low resistance Ohmic contact of n-GaN. The Ge interlayer is acted as heavily n-type dopant atoms at the interface of metal and n-GaN to enhance carrier tunneling. The patterned substrate is designed to increase the annealing temperature at the interface of the metal and n-GaN. Contact resistances were derived from the plot of the measured resistance versus gap spacing by TLM (Transmission Line Model). After annealing at 400 °C for 5mins, It is shown that, Al (300nm)/Ti (30nm)/Ge (10nm)/ pit-patterned n-GaN substrate scheme exhibit ohmic contact behavior with a resistivity of 3.49×10-5 Ω-cm2. The low contact resistance is formed by Al (300nm)/Ti (30nm)/Ge (10nm)/pit-patterned n-GaN substrate scheme, and it is compare with Al (300nm)/Ti (30nm)/n-GaN substrate. Therefore, this results show that utilizing Ge interlayer and patterned substrate could serve as an important processing tool for forming low-resistance Ohmic contacts of n-GaN.
Keywords :
"Annealing","Substrates","Silicon","Ohmic contacts","Resistance","Resists","Current measurement"
Publisher :
ieee
Conference_Titel :
Nanoelectronics Conference (INEC), 2014 IEEE International
Electronic_ISBN :
2159-3531
Type :
conf
DOI :
10.1109/INEC.2014.7460449
Filename :
7460449
Link To Document :
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