Integrating a low-power objective into the placement of macro block-based layouts

Author

Jiménez, Manuel A. ; Shanblatt, Michael

Author_Institution

Dept. of Electr. & Comput. Eng., Puerto Rico Univ., Mayaguez, Puerto Rico

Volume

1

fYear

2001

fDate

2001

Firstpage

62

Abstract

A placement methodology for power optimizing macro block-based VLSI layouts is presented. This technique uses simulated annealing to target solutions with reduced switched capacitance. Its implementation is shown to be consistent and capable of producing competitive layouts whose quality is maintained when problem sizes are scaled up. The results obtained on a set of MCNC benchmarks indicate that power reductions over 16% are possible with increases of less than 1% in delay and total wirelength

Keywords

VLSI; circuit optimisation; integrated circuit layout; low-power electronics; simulated annealing; switched capacitor networks; VLSI layout; low-power design; macro block; placement optimization; simulated annealing; switched capacitance; Capacitance; Computational modeling; Constraint optimization; Delay; Equations; Optimization methods; Power dissipation; Simulated annealing; Switching circuits; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on

Conference_Location

Dayton, OH

Print_ISBN

0-7803-7150-X

Type

conf

DOI

10.1109/MWSCAS.2001.986115

Filename

986115