Title :
Design of a 3.3 V high frequency CMOS VCO with an arithmetic functionality
Author :
Han, Yun Cheol ; Yoon, Kwang Sub
Author_Institution :
Dept. of Electron. Eng., Inha Univ., Inchon, South Korea
Abstract :
In recent years, the design of CMOS VCO at ever-higher frequencies has gained interest. This paper proposes an arithmetic functionality VCO circuit based on a differential ring oscillator for operating in high frequency. The proposed VCO architecture with half adder is able to produce two times higher frequency with any delay cell than conventional VCO. Simulation results show that the proposed VCO produce double oscillation frequency and power dissipation is 14.59 mW
Keywords :
CMOS analogue integrated circuits; adders; low-power electronics; voltage-controlled oscillators; 14.59 mW; 3.3 V; CMOS VCO design; arithmetic functionality; circuit simulation; delay cell; differential ring oscillator; half-adder; high frequency operation; power dissipation; Adders; Arithmetic; Circuits; Consumer electronics; Delay; Frequency; Phase locked loops; Power dissipation; Ring oscillators; Voltage-controlled oscillators;
Conference_Titel :
Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on
Conference_Location :
Dayton, OH
Print_ISBN :
0-7803-7150-X
DOI :
10.1109/MWSCAS.2001.986178
