Adiabatic pseudo-domino logic with dual-rail inputs

Author

Wong, H.H. ; Lau, K.T.

Author_Institution

Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore

Volume

fYear

2001

fDate

2001

Firstpage

340

Abstract

Balanced evaluation branches for dual-rail logic are essential not only to minimize the power dissipation but also to improve the operating frequency of the circuit. In this paper, a fully dual-rail input signaling structure is adopted for the APDL family, even though it increases the number of the transistors in the original circuit. HSPICE simulation shows that DAPDL shift register dissipates 6 times lesser energy than its static CMOS counterpart

Keywords

CMOS logic circuits; SPICE; low-power electronics; shift registers; APDL circuit; CMOS technology; DAPDL shift register; HSPICE simulation; adiabatic pseudo-domino logic; dual-rail input signaling structure; dual-rail logic; power dissipation; CMOS logic circuits; Clocks; Energy consumption; Energy dissipation; Frequency; Logic circuits; Logic devices; Power dissipation; Power engineering and energy; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on

Conference_Location

Dayton, OH

Print_ISBN

0-7803-7150-X

Type

conf

DOI

10.1109/MWSCAS.2001.986182

Filename

986182

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=377142