Title :
Optimized parallel implementation of polynomial approximation math functions on a DSP processor
Author :
Yang, Mei ; Wang, Jinchu ; Wang, Yuke ; Zheng, S.Q.
Author_Institution :
Dept. of Comput. Sci., Texas Univ., Richardson, TX, USA
Abstract :
This paper presents a general method to implement polynomial approximation math functions on TMS320C67X architecture with multiple parallel execution units. Our method consists of grain packing, mapping and scheduling to reduce data dependency overhead and fully utilize delay slots. Experimental results of our method on TMS320C67x have achieved up to 70.2% performance improvement over ´C67x library functions
Keywords :
digital signal processing chips; parallel architectures; polynomial approximation; processor scheduling; ´C67x library function; DSP processor; TMS320C67x architecture; data dependency; delay slot; grain packing; mapping; mathematical function; optimized parallel processing; polynomial approximation; scheduling; Clocks; Computer architecture; Delay; Digital signal processing; Digital signal processing chips; Libraries; Polynomials; Processor scheduling; Registers; VLIW;
Conference_Titel :
Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on
Conference_Location :
Dayton, OH
Print_ISBN :
0-7803-7150-X
DOI :
10.1109/MWSCAS.2001.986183
