Title :
Prototyping design of a transceiver for the new double bitrate DECT
Author :
López, J.A. ; Carreras, C. ; Nieto-Taladriz, O.
Author_Institution :
ETSI Telecomunicacion, Univ. Politecnica de Madrid, Spain
Abstract :
This paper presents the prototyping process for the implementation of the digital blocks of a wireless DECT transceiver that doubles the bit rate of the standard, placing special emphasis on the methodologies developed for architecture generation and wordlength validation. Some implementation results are also given at the end of the paper
Keywords :
circuit CAD; cordless telephone systems; field programmable gate arrays; formal verification; high level synthesis; integrated circuit design; timing; transceivers; OR3T125 FPGAs; TMX320C6201 DSP; VHDL description; architecture generation; digital blocks; double bitrate DECT; high level architecture; high-throughput requirements; platform PCB; prototyping design; wireless DECT transceiver; wordlength validation; Bit rate; Circuits; Clocks; Delay estimation; Discrete event simulation; Prototypes; Standards development; Telecommunications; Timing; Transceivers;
Conference_Titel :
Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on
Conference_Location :
Dayton, OH
Print_ISBN :
0-7803-7150-X
DOI :
10.1109/MWSCAS.2001.986189
