Optimal clock distribution with an array of phase-locked loops for multiprocessor chips

This paper discusses clock distribution for chips with multiple microprocessor cores. A model for clock distribution with an array of phase-locked loops (PLLs) is introduced. The model is used to derive an analytical expression describing the optimal design tradeoff between power dissipation and clock inaccuracy. With parameters typical for a 180-nm fabrication technology, a single PLL is optimal. Distributing the clock with multiple PLLs will not be interesting for the 130-nm technology generation either. At the 100-nm node, the emergence of chips with four PLLs is projected