Title :
Configurable computing and sonar processing - architectures and implementations
Author :
Nelson, Brent E.
Author_Institution :
Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA
Abstract :
Sonar beamforming is an ideal application for reconfigurable computing due to its high available levels of parallelism, relatively low sample rates and modest word sizes. We describe a family of beamforming algorithms and their implementation using configurable computing technology. These include algorithms for time-delay, frequency-domain and matched field beamforming. Configurable computing architectures appropriate for each are described and the tradeoffs associated with the mapping of each to concrete platforms is discussed.
Keywords :
array signal processing; field programmable gate arrays; parallel processing; pipeline processing; reconfigurable architectures; sonar signal processing; FPGA technology; algorithm reformulation; application-specific DSP solutions; configurable computing; fixed-function blocks; frequency-domain beamforming; matched field beamforming; parallel processing; parallelism levels; pipelining; sample rates; sonar arrays; sonar beamforming; sonar processing; time-delay beamforming; word sizes; Array signal processing; Computer architecture; Digital signal processing; Distributed computing; Field programmable gate arrays; Logic arrays; Military computing; Parallel processing; Sonar; Wires;
Conference_Titel :
Signals, Systems and Computers, 2001. Conference Record of the Thirty-Fifth Asilomar Conference on
Conference_Location :
Pacific Grove, CA, USA
Print_ISBN :
0-7803-7147-X
DOI :
10.1109/ACSSC.2001.986880