FPGA implementation of a 3GPP turbo codec

Author

Steensma, Johannes ; Dick, Chris

Author_Institution

Adelante Technol., Melbourne, FL, USA

Volume

1

fYear

2001

fDate

4-7 Nov. 2001

Firstpage

61

Abstract

This paper describes the FPGA implementation of a 3GPP compliant TCC (turbo convolutional codes) codec. The decoder employs the MAP algorithm, utilizing the max* operator, and achieves a BER of 10/sup -6/ for a 1.5 dB SNR. In addition to providing an overview of the datapath architecture, the C based design and verification methodology is presented.

Keywords

C language; cellular radio; codecs; convolutional codes; error statistics; field programmable gate arrays; logic design; maximum likelihood decoding; maximum likelihood estimation; turbo codes; 3G wireless systems; 3GPP codec; BER; C based design methodology; C based verification methodology; FPGA; MAP algorithm; MAP decoding; SNR; base transceiver stations; convolutional codes; datapath architecture; field programmable gate arrays; parallel architecture; turbo codes; Bit error rate; Codecs; Computer architecture; Concatenated codes; Convolutional codes; Design methodology; Field programmable gate arrays; Iterative decoding; Signal processing algorithms; Turbo codes;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 2001. Conference Record of the Thirty-Fifth Asilomar Conference on

Conference_Location

Pacific Grove, CA, USA

ISSN

1058-6393

Print_ISBN

0-7803-7147-X

Type

conf

DOI

10.1109/ACSSC.2001.986881

Filename

986881