Evaluation of complexity and delay of arithmetic circuits as CMOS realizations

Author

Preuber, Thomas B. ; Swartzlander, Earl E., Jr.

Author_Institution

Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA

Volume

1

fYear

2001

fDate

4-7 Nov. 2001

Firstpage

165

Abstract

This paper addresses the realization of digital arithmetic circuits in CMOS, the currently most important technology for integrated circuit implementations. Concrete designs of the basic arithmetic circuits like those of half adders, full adders, ripple carry, carry lookahead and conditional sum adders are investigated. Simple mappings from gate-level designs to CMOS realizations and optimized CMOS implementations are examined and compared in terms of their circuit complexities and latencies.

Keywords

CMOS digital integrated circuits; adders; circuit complexity; delays; digital arithmetic; logic design; CMOS realizations; carry lookahead; circuit complexity; conditional sum adders; delay; digital arithmetic circuits; full adders; gate-level designs; half adders; integrated circuit implementations; ripple carry; Adders; CMOS digital integrated circuits; CMOS integrated circuits; CMOS technology; Complexity theory; Concrete; Delay; Design optimization; Digital arithmetic; Integrated circuit technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 2001. Conference Record of the Thirty-Fifth Asilomar Conference on

Conference_Location

Pacific Grove, CA, USA

ISSN

1058-6393

Print_ISBN

0-7803-7147-X

Type

conf

DOI

10.1109/ACSSC.2001.986899

Filename

986899