An Evaluation Approach on SET Pulse Width

In this paper, analysis of SET pulse effects on circuits have been carried on, and an evaluation model is proposed. This model allows us to calculate a node´s SET pulse width, as a function of the collected charge and the gates´ sizes composing the driving and fan-out logic. A SET simulation is taken with 130nm CMOS process and the result demonstrates the maximal error rate between the measure results by using HSPICE simulation and the calculating results by using this model is almost 6.89%. This developed approach avoids time-costly electrical level simulation under a given technology and power supply, thus implementing great efficiency and speed.