Design and implementation of binary and quaternary low power selective circuit using single electron transistor

This paper presents the performance analysis of single electron transistor(SET) low power Arithmetic & Logical selective Unit. SET which is low power device is used to produce new features, which is nearly impossible to achieve with only CMOS circuit. Efficient SET 4:1 MUX is designed & verified as well as quaternary selective circuit is proposed. As well one bit full adder, AND, OR and XOR is verified. For simulation a spice, OrCAD, and Matlab is used. The Single Electron Transistors are smaller in size, operate at a greater speed and have low power consumption when compared to CMOS.