• DocumentCode
    3774602
  • Title

    Centip3De: A 64-core, 3D stacked, near-threshold system

  • Author

    Ronald G. Dreslinski;David Fick;Bharan Giridhar;Gyouho Kim;Sangwon Seo;Matthew Fojtik;Sudhir Satpathy;Yoonmyung Lee;Daeyeon Kim; Nurrachman Liu;Michael Wieckowski; Gregory Chen;Trevor Mudge;Dennis Sylvester;David Blaauw

  • Author_Institution
    University of Michigan, United States
  • fYear
    2012
  • Firstpage
    1
  • Lastpage
    30
  • Abstract
    This article consists of a collection of slides from the author´s conference presentation on Centip3De, a 64-core, three dimensional (3D) stacked near-threshold system. Some of the specific topics discussed include: power management considerations with processor performance; threshold computing and design; architectural impact of near threshold computing (NTC) versus large scale 3D CMP; NTC architectures; cache timing analysis; system specifications and design of the Centip3De system; evaluation of 2-layer stacking processing; DRAM chips; and multiprocessing systems.
  • Keywords
    "Logic gates","Microprocessors","Three-dimensional displays","Transistors","Voltage control","Capacitance","Threshold current","Performance evaluation"
  • Publisher
    ieee
  • Conference_Titel
    Hot Chips 24 Symposium (HCS), 2012 IEEE
  • Type

    conf

  • DOI
    10.1109/HOTCHIPS.2012.7476490
  • Filename
    7476490
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3774602