Title :
The Intel® Xeon® processor E5 family architecture, power efficiency, and performance
Author :
Jeff Gilbert;Mark Rowland
Abstract :
Presents a collection of slides covering the following topics: Sandy Bridge core; SNB-EP performance; Thurley platform; CPU; DRAM; and memory latency optimization.
Keywords :
"Microprocessors","Optimization","Benchmark testing","Energy efficiency","Power system management"
Conference_Titel :
Hot Chips 24 Symposium (HCS), 2012 IEEE
DOI :
10.1109/HOTCHIPS.2012.7476501
