DocumentCode :
3774624
Title :
Tera-scale computing and interconnect challenges - 3D stacking considerations
Author :
Jerry Bautista
Author_Institution :
Microprocessor Technology Management, USA
fYear :
2008
Firstpage :
1
Lastpage :
34
Abstract :
This article consists of a collection of slides from the author´s conference presentation. Discusses tera-scale computing and interconnect challenges. Suggests that 3D stacking is an attractive solution for both a large last level cache and increasing bulk DRAM capacities.
Keywords :
"Stacking","Performance evaluation","Microprocessors","Wafer bonding","Multicore processing","Through-silicon vias","Bandwidth"
Publisher :
ieee
Conference_Titel :
Hot Chips 20 Symposium (HCS), 2008 IEEE
Type :
conf
DOI :
10.1109/HOTCHIPS.2008.7476514
Filename :
7476514
Link To Document :
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