• DocumentCode
    3774698
  • Title

    An ultra high performance scalable DSP family for multimedia

  • Author

    Erik Machnicki

  • fYear
    2005
  • Firstpage
    1
  • Lastpage
    22
  • Abstract
    This article consists of a collection of slides from the author´s conference presentation. The author reports the following for this product: Multicore Architecture for Media Processing (16 DSP cores optimized for video/media: SIMD, SAD, PIMAC with up to 89.6 GMACs (8×8); State-of-the-Art Development Tools (Graphical multiprocessor debugger/profiler and Multiprocessor dynamic scheduling and run time analysis); and overall High Performance (1 H.264 D1, or 16 MPEG4 CIF channels, encode With resources to spare for audio, intelligent video, I/O, etc. making this a true single-chip solution).
  • Keywords
    "Digital signal processing","Instruction sets","Media","Computational modeling","Scalability"
  • Publisher
    ieee
  • Conference_Titel
    Hot Chips XVII Symposium (HCS), 2005 IEEE
  • Type

    conf

  • DOI
    10.1109/HOTCHIPS.2005.7476589
  • Filename
    7476589