Title :
Ascenium: A continuously reconfigurable architecture
Abstract :
This article consists of a collection of slides from the author´s conference presentation on the special features, system design and architectures, processing capabilities, and targeted markets for Ascenium´s reconfigurable processors.
Keywords :
"Parallel processing","Reconfigurable logic","Bandwidth","Reconfigurable architectures","Computational efficiency","Microprocessors","Program processors"
Conference_Titel :
Hot Chips XVII Symposium (HCS), 2005 IEEE
DOI :
10.1109/HOTCHIPS.2005.7476597
