• DocumentCode
    3775003
  • Title

    Low-power, high-performance architecture of the PWRficient processor family

  • Author

    Tse-Yu Yeh

  • Author_Institution
    Architecture & Verification, USA
  • fYear
    2006
  • Firstpage
    1
  • Lastpage
    29
  • Abstract
    This article consists of a collection of slides from the author´s conference presentation on PASEMI´s PWRficient processor family of products. Some of the specific topics discussed include: PWRficient low power, high performance architecture; design and system specifications; core processing capabilities; and key product offerings and applications supported.
  • Keywords
    "Computer architecture","Voltage control","Process control","Product design","Random access memory","Central Processing Unit","Performance evaluation","Microprocessors"
  • Publisher
    ieee
  • Conference_Titel
    Hot Chips 18 Symposium (HCS), 2006 IEEE
  • Type

    conf

  • DOI
    10.1109/HOTCHIPS.2006.7477746
  • Filename
    7477746
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3775003