Title :
IBM zEC12 processor subsystem
Author :
Robert Sonnelitter
Author_Institution :
System z Processor Development, Systems & Technology Group, IBM Corp., United States
Abstract :
The IBM zEC12 has a robust, multi-level shared cache hierarchy that is designed to meet the needs of the enterprise class computing environment and represents a significant growth in system capacity and performance from its predecessor.
Keywords :
"Topology","Cache storage","Benchmark testing","Program processors","Time factors","Operating systems"
Conference_Titel :
Hot Chips 25 Symposium (HCS), 2013 IEEE
DOI :
10.1109/HOTCHIPS.2013.7478304
