DocumentCode :
3775206
Title :
Programming the Nallatech Xeon + multi-FPGA heterogeneous platform
Author :
Paul Chow;Manuel Salda?a;Arun Patel;Chris Madill
Author_Institution :
University of Toronto, ArchES Computing Systems, Canada
fYear :
2009
Firstpage :
1
Lastpage :
16
Abstract :
Application architecture is abstracted from the implementation by the MPI layer MPI provides a unified programming interface. Hardware implementation can be done without requiring application expertise so that the Application specialist can focus on application design. MPI naturally supports scalability. MPI naturally provides portability. ArchES MPI enables high-performance, multi-core applications for the Nallatech Xeon + multi-FPGA heterogeneous computing platform.
Keywords :
"Program processors","Field programmable gate arrays","Programming","Multicore processing","Coprocessors","Accelerators"
Publisher :
ieee
Conference_Titel :
Hot Chips 21 Symposium (HCS), 2009 IEEE
Type :
conf
DOI :
10.1109/HOTCHIPS.2009.7478369
Filename :
7478369
Link To Document :
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